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Engineering FPGA knowledge base

Articles are linked to boards, chips, toolchains, sources and warnings.

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conceptbeginnerconfidence 4/5
What is an FPGA

An FPGA is configurable digital logic: the design becomes hardware structure after synthesis, place-and-route and bitstream generation.

fpgadigital-logicbitstream
checklistbeginnerconfidence 4/5
How to choose your first FPGA board

Pick the first board by toolchain access, verified examples, documentation, community help and a realistic first project.

boardsbeginnerselection
conceptbeginnerconfidence 4/5
What timing means in FPGA

Timing answers whether signals can travel through logic and routing quickly enough for the target clock and I/O constraints.

timingstaclock
conceptbeginnerconfidence 4/5
From HDL to bitstream

The practical FPGA flow is lint/simulation, synthesis, constraints, place-and-route, timing, bitstream, programming and board validation.

flowsynthesispnrbitstream
toolchain_guidebeginnerconfidence 4/5
What Yosys and nextpnr are

Yosys is an open-source synthesis tool; nextpnr is a portable place-and-route tool supporting several FPGA architectures through device databases.

yosysnextpnropen-source
toolchain_guidebeginnerconfidence 4/5
What Vivado is

Vivado is AMD's FPGA design suite for modern Xilinx/AMD FPGA and SoC families.

vivadoamd-xilinxtoolchain
toolchain_guidebeginnerconfidence 4/5
What Quartus is

Quartus Prime is Intel's FPGA design suite for Intel/Altera FPGA, CPLD and SoC FPGA devices.

quartusintel-fpgatoolchain
toolchain_guidebeginnerconfidence 4/5
What Gowin EDA is

Gowin EDA is the vendor flow for Gowin FPGA families used by Tang and Gowin starter boards.

gowintoolchaintang
board_guidebeginnerconfidence 4/5
iCEBreaker: where to start

Install the open iCE40 flow, run the LED example, verify PCF constraints and then add Pmod experiments.

icebreakerice40open-source
conceptbeginnerconfidence 4/5
How to read an FPGA part number

FPGA order codes encode family, density, package, speed grade, temperature range and sometimes feature variants.

part-numbermpndecoder
checklistbeginnerconfidence 4/5
How to verify pinout

Pinout verification means matching board revision, schematic, FPGA package, bank voltage, connector map and constraint file before connecting hardware.

pinoutconstraintsbring-up
troubleshootingbeginnerconfidence 4/5
Common beginner FPGA mistakes

Most beginner failures come from missing constraints, misunderstood clocks, latch inference, multiple drivers, skipped simulation and wrong board variant.

debugbeginnerpitfalls
toolchain_guidebeginnerconfidence 5/5
What GHDL is

GHDL is an open-source VHDL simulator and synthesis-related tool used in VHDL verification and open FPGA flows.

ghdlvhdlsimulation
protocol_notebeginnerconfidence 4/5
UART in FPGA projects

UART is the simplest board-visible debug channel, but it still needs clock-derived baud timing, synchronizers and a testbench.

uartdebugprotocol
project_templateintermediateconfidence 4/5
RISC-V softcore on FPGA

A RISC-V softcore project needs enough logic, memory, a debug path, firmware build flow and a board-specific memory/IO map.

risc-vsoftcoresoc
checklistprofessionalconfidence 4/5
Linux-on-FPGA board requirements

Linux-capable FPGA projects need a CPU subsystem or large softcore, external memory, storage or boot media, console and a reproducible software build.

linuxsocmemory
vendor_noteintermediateconfidence 4/5
FPGA Board Repository analysis for fpga.camp

The reference is valuable for JSON records, schema validation, part decoding, filters, comparison and PR workflow; fpga.camp adds multilingual knowledge graph behavior.

boardsdata-modelmoderation

Glossary

FPGA

Field-programmable gate array: configurable digital logic fabric programmed after manufacturing.

CPLD

Programmable logic device usually smaller and more deterministic than an FPGA.

LUT

Look-up table used as a basic FPGA logic element.

Flip-flop

Sequential storage element usually clocked by a clock edge.

BRAM

Dedicated block memory inside FPGA fabric.

DSP block

Dedicated arithmetic block for operations such as multiplication and accumulation.

PLL

Clock management block used to generate or condition clocks.

Bitstream

Configuration data loaded into an FPGA to realize a design.

Synthesis

Conversion of HDL into a gate-level or technology-mapped representation.

Place-and-route

Mapping logic to physical locations and routing signals between them.

Static timing analysis

Timing analysis that checks paths against constraints without dynamic simulation.

Slack

Timing margin between required and actual path timing.

CDC

Clock domain crossing; transfer of signals between different clock domains.

Metastability

Unstable state of a sequential element when setup or hold assumptions are violated.

Constraint file

File describing pin assignments, clocks, I/O standards and timing constraints.

XDC

AMD/Xilinx Design Constraints format used by Vivado.

SDC

Synopsys Design Constraints format used by multiple FPGA tools.

PCF

Physical constraints format commonly seen in open iCE40 flows.

QSF

Quartus Settings File used in Intel FPGA projects.

CST

Constraint format used in Gowin FPGA projects.

Pmod

Small expansion connector ecosystem popular on educational FPGA boards.

FMC

FPGA Mezzanine Card connector standard for expansion modules.

JTAG

Debug and programming interface used by many FPGA boards.

UART

Asynchronous serial interface often used for simple board debug.

SPI

Synchronous serial interface commonly used for flash and peripheral chips.

I2C

Two-wire serial bus often used for low-speed control devices.

AXI

AMBA interconnect protocol family widely used in SoC FPGA designs.

Wishbone

Open interconnect bus used in many open-source FPGA SoC projects.

Softcore CPU

Processor implemented in FPGA fabric rather than as hardened silicon.

RAG

Retrieval-augmented generation; answering with retrieved source-backed context.

KB articles and catalog records use sources, verification dates, and confidence levels. Data policy