YADRO and FPGA-Systems: materials from 2021–2026
Meeting recordings and presentations, SoC Design Challenge results and FPGA workshop materials.
Completed events from 2021–2026: 20 event or session pages and 75 material links.
Full-material access is unconfirmed for 54 links. Each event page shows the access status.
FPGA-Systems 2021 supported by YADRO — Moscow
Recordings of the 27 November 2021 conference: FPGA verification, NanoXplore, an FPGA mezzanine, Simtera, VUnit and a Kria carrier board.
FPGA-Systems 2021 supported by YADRO — Saint Petersburg
Recordings of the 4 December 2021 conference: SystemVerilog event regions, Intel Agilex, eFPGA, Simtera, IC testing and high-level synthesis.
YADRO SoC Design Challenge 2022
Archive of the 2022 YADRO and MIET engineering hackathon in Zelenograd: practical digital-design and verification tasks.
YADRO: Touch SoC Development — FPGA workshop 2022
Archive of the YADRO and Sirius University workshop on 3 October 2022: FPGA programming, RISC-V and SoC development at Microelectronics 2022.
FPGA-Systems 2023.1 supported by YADRO — Moscow
Archive of the 1 April 2023 conference: Kria, RTL co-simulation with QEMU and cocotb, Ethernet 10 G, FPGA/ASIC flows and eFPGA.
FPGA-Systems 2023.1 supported by YADRO — Saint Petersburg
Recording of the 8 April 2023 conference: open synthesis tools, remote FPGA access, Pangomicro, FPGA clusters, DEEDS and timing analysis.
YADRO SoC Design Challenge 2023
Archive of the 2023 YADRO and MIET engineering hackathon in Zelenograd: practical digital-design and verification tasks.
FPGA-Systems 2023.2 supported by YADRO — Moscow
25 November 2023 at MIEM and online: LiteX, FPGA bench automation, virtual FPGA, SystemRDL and UVM for DSP. Recording available.
FPGA-Systems 2023.2 supported by YADRO — Saint Petersburg
Recording of the 2 December 2023 conference: virtual FPGA labs, QEMU, Simtera, digital predistortion, chip prototypes and iterative builds.
FPGA-Systems 2023.2 supported by YADRO — Tomsk
Recording of the 9 December 2023 conference: SystemVerilog/VHDL in Quartus and Vivado, SpaceWire, SD cards, Simtera, multiply-add and Drawio HDL Builder.
YADRO ASIC+RTL+FPGA: Minsk meeting, 2 March 2024
Recording and slides on SoC verification, iterative FPGA builds, automated board testing and FPGA clusters.
YADRO SoC Design Challenge 2024
Archive of the 2024 YADRO and MIET engineering hackathon in Zelenograd: practical digital-design and verification tasks.
FPGA-Systems 2024.1 with YADRO — Saint Petersburg
Recording and slides from 25 May 2024: a DDC/DUC transceiver, verification strategy, trusted boot, PyUVM and reusable RTL verification components.
FPGA-Systems 2024.1 with YADRO — Moscow
Recording and slides from the 1 June 2024 conference: SATA on FPGA, AVC/H.264, industrial automation, Simtera and RISC-V.
FPGA-Systems 2024.02 × YADRO — Saint Petersburg
Recording and slides from 26 October 2024: FPGA and ASIC physical design, embedded Linux, prototyping, PyUVM and Simtera.
FPGA-Systems 2024.02 × YADRO — Moscow
Programme, recording and slides from 30 November 2024: Chisel/Scala, UVM, RISC-V, verification, timing and HDMI on FPGA.
YADRO SoC Design Challenge 2025
Archive of the 2025 YADRO and MIET engineering hackathon in Zelenograd: practical digital-design and verification tasks.
FPGA-Systems 2025 with YADRO — Moscow
Recordings from both rooms of the 29 November 2025 conference: RTL, DSP, PCIe prototyping, FPGA-to-ASIC design, verification and physical implementation.
YADRO SoC Design Challenge 2026
Archive of the 2026 YADRO and MIET engineering hackathon in Zelenograd: practical digital-design and verification tasks.
YADRO FPGA community meetup 2026
Recording of the 26 May 2026 meetup: yosys-slang, SystemRDL, register documentation, Edge AI on FPGA and AI-assisted waveform analysis.