AMD engineering webinars: FPGA, SoCs and related design, 2023–2026

Slides and code covering DSP libraries, Model Composer and AI Engine testing on VCK190.

Radio architectures, phased-array modules and the mmWave ecosystem.

Model-based development across programmable logic and AI Engines.

Architecture, polyphase channelizers and FFT implementation on AIE-ML.

Hardware acceleration for direction-of-arrival and spectral estimation.

A system-in-package combining AMD Versal AI Core and Jariet data converters.

Architecture, system integration, Model Composer and DSP examples.

RF converters, digital signal processing and the VRK160 evaluation kit.

Compute, memory and I/O partitioning with Vitis Libraries.

Exploring hardware architectures from the same C/C++ model.

Code profiling and implementation examples in the unified design flow.

Connecting HLS-generated hardware to external memory.

IDE migration, system device trees, Lopper and legacy drivers.

Vitis Metadata Archive files and the hardware–software handoff.

Sequential, pipelined and continuously running hardware modules.

Translating throughput targets into synthesis constraints.

Generating synthesizable C++ with HDL Coder in MATLAB R2025a.

Calling AI Engine graphs and Vitis HLS programmable-logic kernels from MATLAB.

Embedded software support for AMD adaptive SoCs and FPGAs.

High-level synthesis for digital signal processing.

A webinar on combining simulation with hardware execution.

MCP, reusable skills and optimization case studies for FPGA design.

Memory inspection, PS–PL cross triggering and crash analysis.

Clocking architecture, calibrated deskew and the Advanced Flow.

Design iterations, timing closure and available IP blocks.

A step-by-step flow for finding and resolving timing violations.

Simulation of AI Engine and programmable-logic designs before hardware implementation.

MATLAB modelling and RTL comparison for the Zynq UltraScale+ O-RU reference design.

Device selection, power budgets and thermal estimates.

Sensor fusion, AI inference, industrial networking and control.

Core partitioning and virtualization for automotive and embedded visualization.

Processor features, configuration and integration with Vivado and Vitis.

I/O density, power and security in the cost-optimized device family.

Versal HBM acceleration and the AVED design flow for RTL developers.

The memory subsystem and memory-centric acceleration use cases.

Resource use, performance, power, thermal design and timing closure.

I/O, power, security and the cost-optimized device portfolio.

A five-session series on interfaces, power, tools, IP and security.

Power, thermal design, NoC, transceivers, processors and embedded software.

Reference design, low-latency AI inference and FPGA networking.

PCIe Gen4, LPDDR5, transceivers, Ethernet and device security.

PCB design for devices with a fine ball-grid pitch.

Boot, security, monitoring and connectivity for data-center infrastructure.

PCB design with FR4 and through-hole vias for AMD Artix UltraScale+.

Motor control, DSP and development flows for the adaptive system-on-module.

Model-based design and field-oriented control with the K24 module.

Mapping robotics functions to FPGA, SoC, SOM and x86 platforms.

Sensor connectivity, deterministic dataflow and AI inference.

Versal AI Edge Series Gen 2 for inference and automotive post-processing.

Machine vision, deterministic control and sensor processing at the edge.

Project configuration and a first application for the RISC-V soft processor.

Kria AI modules, the robotics development platform and software tools.