AMD FPGA webinars, 2023–2026: materials for 52 events
52 event pages with original dates and links to AMD recording pages. Topics include Vivado, Vitis, HLS, Versal, PCB design and verification. Playback access is unconfirmed.
Multi-session series share one event page. Their date ranges run from the first to the last confirmed programme session.
Vitis developer series: AI Engine design in 2023
DSP libraries, Model Composer, test harnesses and system integration.
AMD Kria K24 and the KD240 Drives Starter Kit
Motor control, DSP and development flows for the adaptive system-on-module.
Kria KD240 motor-control design with MATLAB and Simulink
Model-based design and field-oriented control with the K24 module.
Compiler directives for AMD Vitis HLS
Exploring hardware architectures from the same C/C++ model.
5G mmWave panel with an AMD adaptive-SoC session
Radio architectures, phased-array modules and the mmWave ecosystem.
AMD Power Design Manager for FPGAs and adaptive SoCs
Device selection, power budgets and thermal estimates.
AMD Embedded+: Ryzen and Versal on one board
Sensor fusion, AI inference, industrial networking and control.
AMD robotics hardware and software: webinar series
Mapping robotics functions to FPGA, SoC, SOM and x86 platforms.
Arm Mali GPU integration in AMD Versal Gen 2
Core partitioning and virtualization for automotive and embedded visualization.
Versal AI Engine design with Simulink and Model Composer
Model-based development across programmable logic and AI Engines.
C++ algorithms for FPGA hardware with AMD Vitis HLS
Code profiling and implementation examples in the unified design flow.
AMD FPGAs and adaptive SoCs for machine vision
Sensor connectivity, deterministic dataflow and AI inference.
AMD MicroBlaze V: RISC-V soft processor
Processor features, configuration and integration with Vivado and Vitis.
AMD Spartan UltraScale+ FPGA architecture
I/O density, power and security in the cost-optimized device family.
AMD Versal AI Engines for DSP: webinar series
Architecture, polyphase channelizers and FFT implementation on AIE-ML.
M_AXI interfaces in AMD Vitis HLS
Connecting HLS-generated hardware to external memory.
AMD Alveo V80 for memory-intensive workloads
Versal HBM acceleration and the AVED design flow for RTL developers.
Migrating to AMD Vitis Unified IDE: two-part series
IDE migration, system device trees, Lopper and legacy drivers.
Automotive AI and functional safety with AMD Versal
Versal AI Edge Series Gen 2 for inference and automotive post-processing.
CXL on AMD Versal Premium Series Gen 2
The memory subsystem and memory-centric acceleration use cases.
AMD cost-optimized FPGAs: device and tool comparisons
Resource use, performance, power, thermal design and timing closure.
AMD Spartan UltraScale+ FPGAs: Japanese session
I/O, power, security and the cost-optimized device portfolio.
Exporting AMD Vitis designs to Vivado
Vitis Metadata Archive files and the hardware–software handoff.
AMD cost-optimized FPGAs: device selection and design
A five-session series on interfaces, power, tools, IP and security.
MUSIC signal processing on AMD Versal AI Engines
Hardware acceleration for direction-of-arrival and spectral estimation.
Meeting Fmax targets with AMD Vivado and Versal
Clocking architecture, calibrated deskew and the Advanced Flow.
AMD Vitis HLS execution modes
Sequential, pipelined and continuously running hardware modules.
RF spectrum processing with Mercury RFS1140
A system-in-package combining AMD Versal AI Core and Jariet data converters.
AMD Versal AI Engine development: webinar series
Architecture, system integration, Model Composer and DSP examples.
AMD Versal design tools and architecture: webinar series
Power, thermal design, NoC, transceivers, processors and embedded software.
AMD Alveo V80: AVED and partner implementations
Reference design, low-latency AI inference and FPGA networking.
Performance pragmas in AMD Vitis HLS
Translating throughput targets into synthesis constraints.
MATLAB to AMD Vitis HLS workflow
Generating synthesizable C++ with HDL Coder in MATLAB R2025a.
Vitis functional simulation with MATLAB
Calling AI Engine graphs and Vitis HLS programmable-logic kernels from MATLAB.
Vivado design flow for Spartan UltraScale+ FPGAs
Design iterations, timing closure and available IP blocks.
AMD Versal RF: devices and early RF measurements
RF converters, digital signal processing and the VRK160 evaluation kit.
AMD FPGAs and processors for industrial automation
Machine vision, deterministic control and sensor processing at the edge.
AMD Embedded Development Framework
Embedded software support for AMD adaptive SoCs and FPGAs.
AMD Kintex UltraScale+ Gen 2 FPGA overview
PCIe Gen4, LPDDR5, transceivers, Ethernet and device security.
Zephyr RTOS on AMD MicroBlaze V
Project configuration and a first application for the RISC-V soft processor.
Timing closure for AMD Versal devices
A step-by-step flow for finding and resolving timing violations.
Functional verification of AMD Versal heterogeneous systems
Simulation of AI Engine and programmable-logic designs before hardware implementation.
DSP algorithms in hardware with AMD Vitis HLS
High-level synthesis for digital signal processing.
Designing with 0.5 mm AMD FPGA packages
PCB design for devices with a fine ball-grid pitch.
Vitis subsystem simulation with hardware-in-the-loop and Python
A webinar on combining simulation with hardware execution.
AI-assisted development with AMD Vitis HLS
MCP, reusable skills and optimization case studies for FPGA design.
AMD Spartan UltraScale+ FPGAs in servers and switches
Boot, security, monitoring and connectivity for data-center infrastructure.
Embedded debugging with AMD Vitis Unified IDE
Memory inspection, PS–PL cross triggering and crash analysis.
AMD Kria and Ryzen AI platforms for autonomous robots
Kria AI modules, the robotics development platform and software tools.
Polyphase channelizer optimization on AMD Versal AI Engines
Compute, memory and I/O partitioning with Vitis Libraries.
Routing 0.5 mm FPGA packages without HDI
PCB design with FR4 and through-hole vias for AMD Artix UltraScale+.
Verifying an OpenRAN radio unit on AMD RFSoC DFE
MATLAB modelling and RTL comparison for the Zynq UltraScale+ O-RU reference design.